As the semiconductor industry develops smaller and smaller nanoscale products and processes in pursuit of higher device density, higher performance, and lower costs, the challenges of downscaling both fabrication and design have led to the development of three-dimensional designs, such as multi-gate field effect transistor (FET) including a fin FET (FinFET) and a gate-all-around (GAA) FET. In a FinFET, a gate electrode is positioned adjacent to three side surfaces of a channel region with a gate dielectric layer interposed therebetween. Because the gate structure surrounds the fin on three sides, the transistor essentially has three gates controlling the current through the fin or channel region. However, the fourth side, the bottom part of the channel region, is positioned far away from the gate electrode and thus is not under close gate control. In contrast to a FinFET, a GAA FET includes an arrangement wherein all side surfaces of the channel region are surrounded by the gate electrode, allowing fuller depletion in the channel region and resulting in fewer short-channel effects due to a steeper sub-threshold current swing (SS) and smaller drain induced barrier lower (DIBL).
Although existing GAA FET devices and methods of fabricating GAA FET devices have been generally adequate for their intended purpose, such devices and methods have not been entirely satisfactory in all aspects.